The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to a novel design for a “Steep-Switch” Vertical Field Effect Transistor (SS-VFET).
Traditional CMOS (Complementary Metal Oxide Semiconductor) fabrication techniques include process flows for constructing planar transistors. With planar transistors, transistor density can be increased by decreasing the pitch between transistor gate elements. However, with planar transistors, the ability to decrease gate pitch is limited by the required gate length and spacer thickness. In recent years, there has been significant research and development with regard to nonplanar transistor architectures. Some non-planar transistor architectures, such as Vertical Field Effect Transistors (VFETs), employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. In VFETs the source to drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VFET configuration a major substrate surface is horizontal and a vertical fin or nanowire extends upward from the substrate surface. The fin or nanowire forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin or nanowire sidewalls.